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What is random access memory (RAM)?
Random access memory
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Random access memory or RAM is a type of computer storage whose contents can be accessed in any order. This is in contrast to sequential memory devices such as magnetic tapes, discs and drums, in which the mechanical movement of the storage medium forces the computer to access data in a fixed order. It is usually implied that RAM can be both written to and read from, in contrast to read-only memory or ROM.
Computers use RAM to hold the program code and data during execution. In the first electronic computers, RAM was built from vacuum tubes, and later magnetic cores. The term "core" is still used by some programmers to describe the RAM at the heart of a computer.
Many types of RAM are volatile, which means that unlike some other forms of computer storage such as disk storage and tape storage, they lose their data when the computer is powered down.
Throughout the history of computing, a variety of technologies have been used for RAM, and usually more than one in the same computer, with high-memories constructed out of the same technology as the logic, and slower, cheaper technologies used for bulk storage.
Some early computers used mercury delay lines, in which a series of acoustic pulses were sent along a tube filled with mercury. When the pulse reached the end of the tube, the circuitry detected whether the pulse represented a binary 1 or 0 and caused the oscillator at the beginning of the line to repeat the pulse. Other early computers stored RAM on high-speed "magnetic drums".
Later designs used arrays of small ferrite electromagnets, known as core memory.
Modern RAM generally stores a bit of data as either a charge in a capacitor, as in dynamic RAM, or the state of a flip-flop, as in static RAM.
Common types of RAM
• SRAM or Static RAM
• DRAM or Dynamic RAM
• Fast Page Mode DRAM
• EDO RAM or Extended Data Out DRAM
• SDRAM or Synchronous DRAM
• DDR SDRAM or Double Data Rate Synchronous DRAM
• RDRAM or Rambus DRAM
Not so common types of RAM
• Dual-ported RAM
• Video RAM, a dual-port memory with one random access port and one sequential access port.
Semiconductor RAM is produced as integrated circuits (ICs). RAM ICs are often assembled into plug-in modules. Some standard module types are:
• single-in-line memory module (SIMM)
• dual-in-line memory module (DIMM)
In 1972 some engineers at the Signetics Corporation published a spoof data sheet for a write-only memory. This was a type of RAM with no read facility and therefore no outputs. The full title was Fully Encoded, 9046×N, Random Access Write-Only Memory and the part number was 25120.
Three years ago, there wasn't much to say about sytem RAM. Almost all PCs came with fast page mode (FPM) DRAM, which ran at speeds between 100ns and 80ns. However, escalating CPU and motherboard bus speeds outstripped the ability of FPM DRAM to deliver data in a timely manner. Nowadays there are a lot of different memory designs.
Due to cost considerations, all but the very high-end (and very expensive) computers have utilized DRAM for main memory. Originally, these were asynchronous, single-bank designs because the processors were relatively slow. Most recently, synchronous interfaces have been produced with many advanced features. Though these high-performance DRAMs have been available for only a few years, it is apparent that they will soon be replaced by at least one of the protocol-based designs, such as SyncLink or the DRDRAM design from Rambus, Inc. and Intel.
Basic DRAM Operation
A DRAM memory array can be thought of as a table of cells. These cells are comprised of capacitors, and contain one or more 'bits' of data, depending upon the chip configuration. This table is addressed via row and column decoders, which in turn receive their signals from the RAS and CAS clock generators. In order to minimize the package size, the row and column addresses are multiplexed into row and column address buffers. For example, if there are 11 address lines, there will be 11 row and 11 column address buffers. Access transistors called 'sense amps' are connected to the each column and provide the read and restore operations of the chip. Since the cells are capacitors that discharge for each read operation, the sense amp must restore the data before the end of the access cycle.
The capacitors used for data cells tend to bleed off their charge, and therefore require a periodic refresh cycle or data will be lost. A refresh controller determines the time between refresh cycles, and a refresh counter ensures that the entire array (all rows) are refreshed. Of course, this means that some cycles are used for refresh operations, and has some impact on performance.
A typical memory access would occur as follows. First, the row address bits are placed onto the address pins. After a period of time the RAS\ signal falls, which activates the sense amps and causes the row address to be latched into the row address buffer. When the RAS\ signal stabilizes, the selected row is transferred onto the sense amps. Next, the column address bits are set up, and then latched into the column address buffer when CAS\ falls, at which time the output buffer is also turned on. When CAS\ stabilizes, the selected sense amp feeds its data onto the output buffer
An asynchronous interface is one where a minimum period of time is determined to be necessary to ensure an operation is complete. Each of the internal operations of an asynchronous DRAM chip are assigned minimum time values, so that if a clock cycle occurs any time prior to that minimum time another cycle must occur before the next operation is allowed to begin.
It should be fairly obvious that all of these operations require a significant amount of time and creates a major performance concern. The primary focus of DRAM manufacturers has been to either increase the number of bits per access, pipeline the various operations to minimize the time required or eliminate some of the operations for certain types of accesses.
Wider I/O ports would seem to be the simplest and cheapest method of improving performance. Unfortunately, a wider I/O port means additional I/O pins, which in turn means a larger package size. Likewise, the additional segmentation of the array (more I/O lines = more segments) means a larger chip size. Both of these issues mean a greater cost, somewhat defeating the purpose of using DRAM in the first place. Another drawback is that the multiple outputs draw additional current, which creates ringing in the ground circuit. This actually results in a slower part, because the data cannot be read until the signal stabilizes. These problems limited the I/O width to 4 bits for quite some time, causing DRAM designers to look for other ways to optimize performance.
Page Mode Access
By implementing special access modes, designers were able to eliminate some of the internal operations for certain types of access. The first significant implementation was called Page Mode access.
Using this method, the RAS\ signal is held active so that an entire 'page' of data is held on the sense amps. New column addresses can then be repeatedly clocked in only by cycling CAS\. This provides much faster random access reads, since the row address setup and hold times are eliminated.
While some applications benefit greatly from this type of access, there are others that do not benefit at all. The original Page Mode was improved upon and replaced very quickly so you will likely never see any memory of this type. Even if you do, it wouldn't be worth even getting it for free, considering the advantages of later access modes.
Fast Page Mode
Fast Page mode improved upon the original page mode by eliminating the column address setup time during the page cycle. This was accomplished by activating the column address buffers on the falling edge of RAS\ (rather than CAS\). Since RAS\ remains low for the entire page cycle, this acts as a transparent latch when CAS\ is high, and allows address setup to occur as soon as the column address is valid, rather than waiting for CAS\ to fall.
Fast Page mode became the most widely used access method for DRAMs, and is still used on many systems. The benefit of FPM memory is reduced power consumption, mainly because sense and restore current is not necessary during page mode access. Though FPM was a major innovation, there are still some drawbacks. The most significant is that the output buffers turn off when CAS\ goes high. The minimum cycle time is 5ns before the output buffers turn off, which essentially adds at least 5ns to the cycle time.
Today, FPM memory is the least desirable of all available DRAM memory. You should only consider using this if it is either free, or your system does not support any of the later memory types (such as a 486 based system). Typical timings are 6-3-3-3 (initial latency of 3 clocks, with a 3-clock page access). Due to the limited demand, FPM is actually more expensive now than most of the faster memories now available.
Once it became apparent that bus speeds would need to run faster than 66MHz, DRAM designers needed to find a way to overcome the significant latency issues that still existed. By implementing a synchronous interface, they were able to do this and gain some additional advantages as well.
With an asynchronous interface, the processor must wait idly for the DRAM to complete its internal operations, which typically takes about 60ns. With synchronous control, the DRAM latches information from the processor under control of the system clock. These latches store the addresses, data and control signals, which allows the processor to handle other tasks. After a specific number of clock cycles the data becomes available and the processor can read it from the output lines.
Another advantage of a synchronous interface is that the system clock is the only timing edge that needs to be provided to the DRAM. This eliminates the need for multiple timing strobes to be propagated. The inputs are simplified as well, since the control signals, addresses and data can all be latched in without the processor monitoring setup and hold timings. Similar benefits are realized for output operations as well.
HyperPage Mode (EDO)
The last major improvement to asynchronous DRAMs came with the Hyperpage mode, or Extended DataOut. This innovation was simply to no longer turn off the output buffers upon the rising edge of /CAS. In essence, this eliminates the column precharge time while latching the data out. This allows the minimum time for /CAS to be low to be reduced, and the rising edge can come earlier.
In addition to a 40% or greater improvement in access times, EDO uses the same amount of silicon and the same package size. EDO has been shown to work well with memory bus speeds up to 83MHz with little or no performance penalty. If the chips are sufficiently fast (55ns or faster), EDO can be used even with a 100MHz memory bus. One of the best reasons to use EDO is that all of the current motherboard chipsets support it with no compatibility problems, unlike much of the synchronous memory now being used.
Even with all the stated advantages, EDO is no longer considered mainstream. Most manufacturers no longer produce it, or have limited production. It is only a matter of time before the prices begin to rise, and the equivalent size SDRAM module will be less expensive.
If you already own EDO memory, there is no real reason to jump to SDRAM unless you require bus speeds above 83MHz. With a typical EDO timing of 5-2-2-2 at 66MHz, there is almost no noticeable improvement with SDRAM over EDO, and at 83MHz it is still negligible. If you require 100MHz bus operation, EDO will lag far behind current SDRAM in performance even if it does operate at that speed due to the need for 6-3-3-3 timings. On the other hand, with EDO being phased out, you will likely find SDRAM to be equal to or even lower in price.
Burst EDO (BEDO)
Burst EDO, while a good idea, was dead before it ever was born. The addition of a burst mode, along with a dual bank architecture would have provided the 4-1-1-1 access times at 66MHz that many expected with SDRAM. Burst mode is an advancement over page mode, in that after the first address input, the next 3 addresses are generated internally, thereby eliminating the time necessary to input a new column address. Unfortunately, Intel decided that EDO was no longer viable, and SDRAM was their preferred memory architecture so they did not implement support of BEDO into their chipsets. In fact, several large memory manufacturers had put considerable time and money into the development of SDRAM over the past decade, and were not very happy with the BEDO design.
Except for support of bus speeds of 100MHz and faster, BEDO would probably have been a much faster and more stable memory than SDRAM. Essentially, BEDO lost support as much for political and economic reasons as for technical ones, it seems.
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